1. Field of the Invention
The present invention relates to a static random access memory (SRAM) with address transition detector (ATD).
2. Description of the Related Art
The SRAM is described in, for example, IEEE Journal of Solid-State Circuits, Vol. SC-19, No. 5, October 1984, "A LOW POWER 46ns 256kbit CMOS STATIC RAM WITH DYNAMIC DOUBLE WORD LINE", Sakurai et al., and 1987 IEEE Journal of Solid-State Circuits Conference DIGEST OF TECHNICAL PAPERS "A 25ns 1Mb CMOS SRAMs" Ohtani et al. The SRAMs discussed in these papers contain ATDs.
In this type of the SRAM, the output stage of a data output circuit is provided with a pull-up transistor for pulling up a potential at the data output terminal, and a pull-down transistor for pulling down the potential at that terminal. In accordance with the data read out from a selected memory cell, one of those transistors is turned on, while the other is turned off. Accordingly, a high level signal or a low level signal is derived from the data output terminal in accordance with the data stored in the selected memory cell. Then, when another memory cell is selected, one of the transistors is turned on, while the other is turned off in accordance with the data read out from the memory. In this case, if the new data is different from the previous data, there is the possibility that the pull-up and pull-down transistors are both turned on concurrently. If both the transistors are currently turned on, a through-current flows through a path between a power source and a ground point. The through-current possibly causes power noise, so that the data read time delays and the memory device malfunctions. These problem is noticeable particularly in the memory device of the type operating at a high speed.